1. Field of the Invention
This invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM), or a static random access memory (SRAM), and more particularly to a semiconductor memory device in which sense amplifiers conduct the sensing process at high speed so that the access time can be shortened.
2. Description of the Prior Art
FIG. 8 shows a conventional DRAM. The DRAM of FIG. 8 comprises sense amplifiers of the differential type SA0, SA1, . . . , SAn which are arranged in one direction, pairs of bit lines B0 and B0, B1 and B1, . . . , Bn and Bn, and word lines W1, W2, . . . which intersect with the bit lines. At crossings of the bit lines and the word lines W1, W2, . . . , memory cells M are formed which are connected to the bit lines and the word lines W1, W2, . . . , respectively. In the accompanying drawings, for the sake of simplification, P-MOS pull-up transistors for sense amplifiers SA0, SA1, . . . , SAn are omitted, and only a pair of N-MOS pull-down transistors NT1 and NT2 are shown as components of each of the sense amplifier SA0, SA1, . . . , SAn. All of common source terminals S0, S1, . . . , Sn of the N-MOS pull-down transistor pairs NT1 and NT2 are connected a discharge line SAN one end of which is grounded through a transistor Q. Hereinafter, when ones of the sense amplifiers, the bit lines, and the common source terminals are stated as typical examples of these components, these are sometimes referenced by SAi, Bi and Bi, and Si, respectively.
FIG. 9 shows another conventional DRAM. The DRAM of FIG. 9 has the same construction as that of FIG. 8 except that one end of the discharge line SAN is grounded through a parallel circuit of transistors Q1 and Q2. The conductance of the transistor Q1 is smaller than that of the transistor Q2.
The operation of these DRAMs will be described. When data is to be read from one of the memory cells M, the bit line pairs B0 and B0, . . . , Bn and Bn are charged to an intermediate potential V.sub.cc /2. Then, one of the word lines W1, W2, . . . is selected to be activated in accordance with an input address signal. The memory cells M connected to the selected word line are coupled to the corresponding bit lines Bi or Bi, so that a minute potential difference the degree of which corresponds to the level of the charge stored in the memory cells M appears between the bit lines Bi and Bi. Thereafter, the potential of the discharge line SAN is lowered from the intermediate potential V.sub.cc /2 to the ground level, thereby causing the corresponding sense amplifier SAi to differentially amplify this potential difference. Namely, the potential of one of the bit line pair Bi and Bi which is lower is reduced to zero while that of the other bit line which is higher is maintained. If the potential of the common source terminal Si is rapidly lowered during this process, the sensitivity of the sense amplifier SAi may drop, resulting in a possible malfunction of the sense amplifier.
In order to prevent this phenomenon from occurring, a counter measure is taken in a conventional DRAM. In the DRAM of FIG. 8, as shown in FIG. 10, the gate potential .phi. of the transistor Q is raised at time t.sub.1 to a voltage V.sub.m which is slightly lower than the power source voltage V.sub.cc, and the sense amplifier SAi begins to operate gently (initial amplification). After the potential difference between the bit lines Bi and Bi has sufficiently widened (i.e., after time t.sub.2), the gate potential .phi. is further raised to the power source voltage V.sub.cc, and the sense amplifier SAi performs its full operation (main amplification). In the DRAM of FIG. 9, the two-stage amplification is conducted in order to prevent the sense amplifiers Sai from erroneously operating, as described below. First, as shown in (a) of FIG. 11, the gate potential .phi.'1 of the transistor Q is raised at time t.sub.1 to the power source voltage V.sub.cc so that the transistor Q1 having a smaller conductance is turned on and initial amplification is performed. After the potential difference between the bit lines Bi and Bi has sufficiently widened (i.e., after time t.sub. 2 ((b) of FIG. 11)), the gate potential .phi.'2 of the transistor Q2 is raised to the power source voltage V.sub.cc, whereby the transistor Q2 having a larger conductance is turned on. Thereafter main amplification is performed.
As described above, the common source terminal Si of each sense amplifier SAi is connected to the discharge line SAN at a position nearest to the respective sense amplifier SAi. In the discharge line SAN, portions between these connecting positions function as resistors r. Each of the sense amplifiers SAi exhibits the function of a load capacitance. When the gate potential .phi. or .phi.'1 is raised to turn on the transistor Q or Q1, therefore, the potential of the common source terminal S0 which is closest to the ground GND drops relatively rapidly, and, in contrast, that of the common source terminal Sn which is remotest from the ground GND drops slowly. In other words, in the sense amplifier SAn positioned far from the ground GND, the commencement of initial amplification is delayed. In a conventional semiconductor memory device, consequently, the overall time period required for performing initial amplification in all sense amplifiers (in the above-mentioned DRAMs, the time period from when the gate potential .phi. or .phi.'1 is raised and until when the remotest sense amplifier SAn operates and the potential difference between the bit lines Bn and Bn becomes sufficiently large) is long. This makes the access time longer.